1. Field of the Invention
The present invention relates to a network apparatus having network functions and, more specifically, relates to a network apparatus, a method for controlling the network apparatus, and a program, wherein the network apparatus is capable of switching between buffers for sleep operation and buffers for normal operation.
2. Description of the Related Art
Recently, there has been a demand for reducing the stand-by power required while an apparatus is not in operation (i.e., while the apparatus is in a ‘sleep mode’. Some known apparatuses are capable of reducing the required stand-by power by using two separate control units, wherein a CPU or a controller is used for carrying out the processing required for sleep operation and a main CPU is used for carrying out processing required for normal operation. The power supply to the main CPU is terminated while the apparatus is in a sleep mode (refer to Japanese Patent Laid-Open No. 2000-261515).
By distributing the processing required for such an apparatus between two control units, the processing related to input received from the outside (i.e., the so-called input/output processing) may be carried out by one of the controller units (or CPU). In this way, while in a sleep mode, only the CPU for input/output (I/O CPU) (or controller) will be in operation. However, when there is an input from the outside while in a sleep mode, the apparatus will drive the main CPU required for normal operation so as to return from sleep operation mode to normal operation mode (refer to Japanese Patent Laid-Open No. 11-110089).
When processing required for an apparatus is distributed between two control units, the CPU used as the main CPU should be capable of high-speed processing. Consequently, a high-speed memory is required for the high-speed CPU. Such a high-speed CPU and a high-speed memory consume a large amount of power. However, power consumption of the apparatus in sleep operation can be reduced by stopping the power supply to the main CPU and its memory.
On the other hand, the CPU used as the I/O CPU only needs to be able to carry out minimum processing required for sleep operation. The memory required for such an I/O CPU is often low capacity, low-speed, and low power-consuming.
Network processing for an apparatus having the above-described CPU structure will now be described. Network processing for such an apparatus must be carried out at high speed and requires a relatively high level of CPU power. Since the apparatus must be accessible from a network, it must be operable at all times, including while in a sleep mode.
To satisfy the above-mentioned conditions, the apparatus carries out packet processing with the main CPU and the memory for the main CPU in normal operation, and switches to the I/O CPU in sleep operation. Then, when a predetermined action is carried out or a predetermined packet is received, the apparatus switches back from the I/O CPU to the main CPU to return to normal operation (refer to Japanese Patent Laid-Open No. 2004-34488).
To realize this structure, the apparatus is usually capable of switching buffer regions for storing packets received by a network adapter (also known as a network controller or a local area network (LAN) controller). More specifically, the apparatus stores the packets in the memory for the main CPU while in a normal operation mode, and stores the packets in the memory for the I/O CPU while in a sleep mode.
Although an apparatus using a network controller may be able to switch between two types of buffers for sleep and normal operation, as described above, it is extremely difficult to provide an apparatus that is capable of switching between a sleep mode and a normal operation mode without failing to receive any packets and at the same time, is capable of carrying out high-speed network processing in normal operation and is accessible from a network in sleep operation. From this point of view, known network apparatuses require further improvement.
The present invention has taken into consideration the above-mentioned problems and provides a network apparatus that is capable of switching between two types of buffers for sleep operation and normal operation and capable of receiving packets without failure, and also provides a method for controlling the network apparatus.